Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
FPGAs generally have several types of supply voltage input pins. For example, some FPGAs have VCCO, VCCAUX, and VCCINT as separate types of supply voltages that are provided from one or more external sources via external pins. VCCO is an externally provided supply voltage generally used to power output drivers. VCCAUX is an externally provided supply voltage generally used to power configuration memory, analog blocks, DCMs, and some I/O resources. VCCINT is an externally provided supply voltage, which is generally used to power programmable logic, including CLBs, of an FPGA, namely the “core logic” of an FPGA.
VCCO, VCCAUX, and VCCINT may have different logic high voltage levels. In a conventional FPGA, or other integrated circuit, with multiple supply voltages having different logic high voltage levels, level shifter circuits used N-channel transistors for pull-up voltages. A conventional level shifter circuit may include separate level shifters, where their outputs are respectively coupled to N-channel pull-up transistors. For example, for two level shifters in a level shifter circuit, there may be two N-channel pull-up transistors respectively coupled to the output of the two level shifters. One of these N-channel transistors was conventionally coupled to a voltage supply in a range of approximately 2.5 volts or higher, and the other of these N-channel transistors was conventionally coupled to a voltage supply in a range of approximately 1.0 to 1.2 volts.
Because N-channel transistors were used, they could selectively have their gates coupled to a ground potential to be put in a known state during a power-up operation, commonly known as a “power-on reset” (POR) cycle, as part of a voltage select circuit. Accordingly, such N-channel transistors during a POR cycle were in a state where there was no available channel for conduction, namely “completely shut-off.”
In short, in a system with multiple logic high voltages, it was desirable to use N-channel transistors in a voltage select circuit, because their gates may be coupled to ground to ensure such N-channel transistors are completely shut-off during a POR cycle. With use of N-channel transistors, operation of such a voltage select circuit may be immune from uncertainties in voltage levels of supply voltages as they were powered up during a POR cycle.
In contrast to use of N-channel transistors, P-channel transistors are completely shut-off when their gates are biased to a logic high voltage level which precludes conductivity during a POR cycle. However, during a POR cycle for a system with multiple voltage levels, some supplies may power-up before others which may lead to an unacceptable condition. Thus, P-channel transistors heretofore were not a good choice as they were subject to uncertainties in voltage levels during a POR cycle.
More recently, operational logic high voltage levels have been reduced. For example, a voltage select circuit may have to accommodate differing supply voltages which are both less than 2 volts and which have a less than 0.5 volt difference between them. Unfortunately, conventional N-channel transistors in such voltage select circuits have thick gate dielectrics sufficient for allowing their gate voltages to be driven sufficiently high to allow NMOS to conduct, and thus such conventional N-channel transistors have correspondingly large threshold voltages. Because of the relative size of such threshold voltages of the N-channel transistors in comparison to the lowered supply voltage levels, such N-channel transistors may not be sufficiently conductive when their gates are biased with a logic high voltage level during operation after a POR cycle. In short, using N-channel transistors to implement switches means the control voltage is to be at least a threshold voltage above a channel voltage of such transistors, and this may be an issue when the threshold voltage of thick-oxide N-channel transistors is higher.
Accordingly, it would be desirable and useful to provide a voltage select circuit which overcomes one or more of the above-described limitations for operating with different supply voltage levels both of which are less than 2 volts.